Jobangebote by Dynamic Engineering

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Digital Functional Verification Engineer (m/f/d)

Your Tasks:

• Develop System Verilog UVM based TB and execute verification
• Create feature based vplan
• Create milestone plan for tracking
• Develop System Verilog UVM based environment for CL protocol
• Maintain legacy Specman TB for existing functionality
• Implement testcases
• Implement functional coverage
• Enhance testcases to achieve 100% functional and code coverage
• Run regressions and debug fails
• Provide documentation and handover to junior colleague
• Regular reporting of verification status and progress

Your Profile:

• Knowledge of Digital Design and Verification
• FlowExperience in verification of complex digital designs including TB setup
• 5+ years UVM experience
• Good communication skills
• Cadence Xcelium, Cadence V Manager
• Ideally: Experience with cryptographic modules

If your profile fits the requirements, we are looking forward to receiving your application documents with the mentioned reference number.

Accelerate your career with us
 
As an engineering specialist we take care of all tasks along the value added chain. Whether in our technical offices or in a team on site at our costumers – we support them during the development of complicated, demanding and new challenges. Starting from the entire development processes up to the details.